1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a power supply configuration for sense amplifier circuits sensing and amplifying a memory cell data.
2. Description of the Background Art
FIG. 23 is a diagram schematically showing a construction of a memory mat of a conventional semiconductor device. In FIG. 23, a memory array is divided into a plurality of memory blocks MB#1 to MB#n each including a plurality of memory cells arranged in rows and columns. Sense amplifier bands SB#1 to SB#nxe2x88x921 each are arranged between memory blocks adjacent in a column direction and sense amplifier bands SB#0 and SM#n are arranged outside the memory blocks MB#1 and MB#n, respectively. In each sense amplifier band, sense amplifier circuits are arranged corresponding to columns of the adjacent memory blocks and the sense amplifier circuits are shred between the adjacent memory blocks. A memory array is divided into the plurality of memory blocks MB#1 to MB#n and sense amplifier circuits are arranged on both sides of each of the memory blocks MB#1 to MB#n to make shorter lengths of bit line pairs provided in correspondence to respective memory cell columns in each memory block and thereby loads thereon are reduced, so that a memory cell data at a sufficiently high voltage level is transmitted to a sense amplifier circuit at a high speed and a high-speed sense operation is realized.
In such a memory mat configuration, a power supply voltage and a ground voltage are supplied to the sense amplifier bands SB#0 to SB#n in order that sense amplifiers sense and amplify memory cell data on corresponding columns. In a case where the power supply voltage and the ground voltage are transmitted over a long distance, levels of the power supply voltage and the ground voltage varies due to interconnection line resistance of power source voltage supply lines (including a power supply voltage line and a ground voltage line), whereby no correct sense operation can be performed. Further, with the presence of such interconnection line resistance, the power source voltage (power supply voltage and ground voltage) cannot be supplied to sense amplifiers at a high speed (variations of the power supply voltage cannot be suppressed). Therefore, the power supply line and the ground line are laid on the memory cell array in a meshed shape arrangement in order to supply the sense amplifier power supply voltage and the sense amplifier ground voltage in a stable manner to sense amplifier circuits included in the sense amplifier bands SB#0 to SB#n.
FIG. 24 is a block diagram schematically showing a power supply configuration of a conventional semiconductor memory device. In FIG. 24, a main power supply line MPL is laid out so as to surround the memory mat. Subsidiary power supply lines SBPL are laid out so as to be connected to the main power supply line MPL and extends over the memory blocks MB#1 to MB#n, and over the sense amplifier bands SB#0 to SB#n. In each of the sense amplifier bands SB#0 to SB#n, there is laid out a sense amplifier power supply line SAPL in order to transmit the power supply voltage to the sense amplifier circuits. To the main power supply line MPL, active sense amplifier power supply circuits ACVG1 and ACVG2 made active in an active cycle and generating a sense amplifier power supply voltage VCCA are connected and a standby sense amplifier power supply voltage circuit STVG maintaining a level of the power supply voltage VCCA on the main power supply line MPL is also connected. Here, an active cycle indicates an operating cycle in which rows (word lines) in a predetermined number of blocks among the memory blocks MB#1 to MB#n are each driven to a selected state and the corresponding sense amplifier circuits operate. A standby cycle indicates an operating cycle in which all rows (word lines) in the memory blocks MB#1 to MB#n are held in a non-selected state. In the standby cycle, the active sense amplifier power supply circuits ACVG1 and ACVG2 are held in an inactive state.
With the power supply line and the sense amplifier power supply lines SAPL transmitting the sense amplifier power supply voltage VCCA, laid on the memory mat in a meshed shape arrangement, interconnection line resistance of the sense amplifier power supply lines SAPL provided in the respective sense amplifier bands SB#0 to SB#n are reduced equivalently and further a width of interconnection line is also larger equivalently, thereby enabling the power supply voltage VCCA to be supplied in a stable manner.
In FIG. 24, power supply lines transmitting the sense amplifier power supply voltage VCCA are shown and ground lines transmitting the ground voltage VSS are also laid on the memory mat in a meshed shape arrangement.
With the active sense amplifier power supply circuits ACVG1 and ACVG2 provided, currents are supplied onto the main power supply line MPL, the subsidiary power supply lines SBPL and the sense amplifier power supply lines SAPL from both sides of one end of the memory mat in a stable manner to prevent the power supply voltage of the sense amplifier power supply voltage VCCA from being distributed. Further, the active sense amplifier power supply circuits ACVG1 and ACVG2 are activated when the memory mat enters an active cycle and the sense amplifier circuits in a selected sense amplifier band operate to consume the sense amplifier power supply voltage VCCA, with the result that a level down in the sense amplifier power supply voltage VCCA is prevented from occurring. Therefore, the active sense amplifier power supply circuits ACVG1 and ACVG2 each are required to have at least a capability to compensate for a current consumed in the sense amplifier circuits and thus, have a comparatively large current drive capability.
On the other hand, while the standby sense amplifier power supply circuit STVG operates all time, requirement thereon is only to compensate for reduction in the sense amplifier power supply voltage VCCA caused by a leakage current in the standby cycle and a current drive capability of the standby sense amplifier power supply circuit STVG is small comparatively.
FIG. 25 is a circuit diagram showing a configuration of one sense amplifier circuit and its peripheral circuits included in a sense amplifier band. In FIG. 25, the sense amplifier band SB# is shared between the memory blocks MB#L and MB#R. The sense amplifier circuit includes a sense amplifier SA performing differential amplification of potentials on common bit lines CBL and ZCBL when activated and sense amplifier activation transistors P1 and N1 which become conductive when a sense amplifier activation signal ZSOP and SOP are activated, to transmit the sense amplifier power supply voltage VCCA on the sense amplifier power supply line and the sense amplifier ground voltage VSS on the sense amplifier ground line to the sense amplifier SA. A pair of the sense amplifier activation transistors P1 and N1 are provided commonly to a predetermined number of sense amplifiers. A sense amplifier SA includes P channel MOS transistors P2 and P3 cross-coupled to each other and N channel MOS transistors N2 and N3 cross-coupled to each other.
The sense amplifier SA are connected to bit lines BLL and ZBLL of the memory block MB#L through a bit line isolation gate BIGL and bit lines BLR and ZBLR of the memory block MB#R through a bit line isolation gate BIGR. In the memory block MB#L, a memory cell MC is placed corresponding to an intersection of the word line WLL and the bit line BLL or ZBLL and likewise, in the memory block MB#R, a memory cell MC is placed corresponding to an intersection of the word line WLR and the bit line BLR or ZBLR. In FIG. 25, memory cells MC are placed at the intersections between the word line WLL and the bit line ZBLL and between the word line WLR and the bit line ZBLR. Between the common bit lines CBL and ZCBL, there is provided a bit line equalize circuit BLEQ for precharging the common bit lines CBL and ZCBL, the corresponding bit lines BLR and ZBLR and the corresponding bit lines BLL and ZBLL to a predetermined intermediate voltage level in the standby state.
The bit line isolation gates BIGL and BIGR become conductive in response to bit line isolation instruction signals BLIL and BLIR respectively. Now, description will be given of operation of the sense amplifier circuit shown in FIG. 25 with reference to a signal waveform diagram shown in FIG. 26 simply.
It is assume that the word line WLL is selected in the memory block MB#L. When an active cycle starts, first the bit line isolation instruction signal BLIR falls from H level to L level according to an address signal to place the bit line isolation gate BLIR into the off state. With placement of the bit line isolation gate BLIR into the off state, the bit lines BLR and ZBLR of the memory block MB#R are isolated from the common bit lines CBL and ZCBL. On the other hand, the bit line isolation instruction signal BLIL maintains H level. Then, the word line WLL corresponding to an addressed row by a decode result of an address signal is driven to a selected state, and a voltage level of the word line WLL rises. In general, the selected word line WLL is driven to a level of a boosted voltage Vpp higher than the sense amplifier power supply voltage VCCA.
When the word line WLL is driven to the selected state, an access transistor included in a memory cell MC becomes conductive and a change in potential corresponding to information stored in the memory cell arises on the bit line ZBLL. In FIG. 26, there is shown an example of a signal waveform when a data at H level is read out onto the bit line ZBLL. The bit line BLL maintains an intermediate voltage (VCCA/2) set in a precharged state.
When a potential difference between the bit lines BLL and ZBLL is sufficiently large, sense amplifier activation signals SON and ZSOP are activated to make the sense amplifier activation transistors N1 and P1 conductive, respectively, and the ground voltage VSS and the sense amplifier power supply voltage VCCA are supplied to the sense amplifier SA, whereby the sense amplifier SA starts sensing operation.
The common bit lines CBL and ZCBL are connected to the bit lines BLL and ZBLL through the bit line isolation gate BLIL and by the sensing operation of the sense amplifier SA, the common bit lines CBL and ZCBL, and bit lines BLL and ZBLL are driven to the ground voltage VSS and the sense amplifier power supply voltage VCCA according to a memory data, respectively.
Thereafter, data access to a memory cell (data write/data read) is carried out by a column selection circuit not shown. In the memory block MB#R, the bit line isolation gate BIGR is in the off state and the bit lines BLR and ZBLR maintain the precharged state.
When the active cycle is completed, the selected word line WLL is driven to a non-selected state to turn the access transistor in the memory cell MC into the off state. Then, the sense amplifier activation signals SON and ZSOP are deactivated and the bit line isolation instruction signal BLIR goes to H level, so that the bit lines BLR and ZBLR of the memory block MB#R are connected to the common bit lines CBL and ZCBL. Then, the bit line equalizer BLEQ is activated and the bit lines BLR and ZBLR, BLL and ZBLL, and the common bit lines CBL and ZCBL are precharged to a level of the intermediate voltage (VCCA/2). The semiconductor memory device enters the standby cycle and waits for a next access.
A memory cell MC, as shown in FIG. 27, includes a capacitor MQ to store information, and an access transistor MT which connects the capacitor MQ with a bit line BL (or ZBL). The access transistor MT is constituted of an N channel MOS transistor (insulted gate type field effect transistor) and has a threshold voltage. The maximum voltage on the bit line BL is the sense amplifier power supply voltage VCCA transmitted by the sense amplifier. A boosted voltage Vpp which is sufficiently higher than (usually 1.5 times as high as) the array power supply voltage VCCA is transmitted onto the word lines WL (WLL and WLR) in order to transmit a signal at the array power supply voltage VCCA level to the memory capacitor MQ without any threshold voltage loss across the memory transistor MT. Thereby, the maximum array power supply voltage VCCA is transmitted to the memory capacitor MQ. When a voltage level of the array power supply voltage VCCA lowers, according to this voltage lowering a voltage level of a H level data stored in the memory capacitor MQ lowers. After the access transistor MT has been turned into the off state, a voltage level of the stored data at H level on the memory capacitor decreases gradually by a leakage current of the memory capacitor MQ. In a case where a voltage level of the array power supply voltage VCCA is low, the H voltage level of the stored data of the memory capacitor MQ lowers faster. Therefore, in this case, a charge holding characteristic (refresh characteristic) of the memory cell MC is deteriorated.
Further, when a voltage level of the array power supply voltage VCCA lowers, a voltage level transmitted to a power supply node of the sense amplifier SA lowers, thereby reducing an operating speed of the sense amplifier SA and deteriorating sensitivity thereof as well. With reduction in the sensitivity of sense amplifiers, a sense margin decreases accordingly, whereby there arises a problem that no correct sense operation of a memory cell data is effected. In this case, the memory cell data comes to be destroyed.
Therefore, in order to prevent reduction in sense margin and reduction in voltage level of a H level data in a memory cell from occurring, the power supply configuration in a meshed shape arrangement shown in FIG. 24 is adopted, thereby, resistance of the sense amplifier power supply line is smaller equivalently and a width of the power interconnection line is wider equivalently, so that a stable sense amplifier power supply voltage VCCA is supplied to the sense amplifier.
However, the sense amplifier power supply circuits, as shown in FIG. 24, are arranged at one end of the memory mat and distances from the active sense amplifier power supply circuits ACVG1 and ACVG2 to the memory blocks MB#1 to MB#n are different from one another. For this reason, values of equivalent resistance of sense amplifier power supply lines to the sense amplifier bands SB#0 to SB#n are different from one another. For example, when a sense amplifier operates in the sense amplifier band SA#0 and a voltage level of the sense amplifier power supply line SAPL of the sense amplifier band SB#0 lowers due to a sensing operation, then a current (or electric charge) is supplied from the active sense amplifier power supply circuits ACVG1 and ACVG2 provided at one end of a memory mat. Therefore, since power supply interconnection line resistance is the largest at the sense amplifier band SB#0, a current supply (electric charge supply) thereto is delayed and reduction in sense amplifier power voltage cannot sufficiently be compensated for. On the other hand, the sense amplifier band SB#n is the closest to the active sense amplifier power supply circuits ACVG1 and ACVG2 and equivalent interconnection line resistance of the sense amplifier power supply line is the smallest. In the sensing operation, an electric charge is supplied from the active sense amplifier power supply circuits ACVG1 and ACVG2 at a high speed and reduction in the power supply voltage VCCA can be suppressed, thus ensuring a high speed, correct sensing operation.
In a semiconductor memory device, a holding characteristic of a memory cell data is determined by the worst case. H level of a memory cell data of the memory block MB#1 driven by the sense amplifier bands SB#0 and SB#1 at the farthest positions cannot be restored sufficiently to the sense amplifier power supply voltage level VCCA, thereby deteriorating an electric charge holding characteristic of a memory cell, and further leading to degradation in an electric charge holding characteristic (a refresh characteristic) of a semiconductor memory device as a whole.
It is an object of the present invention to provide a semiconductor memory device whose data holding characteristic is improved.
It is another object of the present invention to provide a semiconductor memory device that can supplies a sense amplifier power supply voltage in a stable manner independently of a position of a sense amplifier band.
It is a further object of the present invention to provide a semiconductor memory device that can suppress reduction in sense amplifier power supply voltage in a uniform manner over a plurality of sense amplifier bands.
A semiconductor memory device according to a first aspect of the present invention includes a memory array including a plurality of memory blocks each having a plurality of memory cells arranged in rows and columns. The plurality of memory blocks are aligned along a column direction.
The semiconductor memory device according to the first aspect of the present invention further includes: a plurality of sense amplifier bands is at least placed between memory blocks adjacent along a column direction, each of which includes a sense amplifier circuit for sensing and amplifying a data on a selected memory cell of a corresponding memory block; and a power supply line laid extending over a plurality of memory blocks and the plurality of sense amplifier bands. The power supply line includes sense amplifier power supply lines each for supplying a power supply voltage to sense amplifier circuits of each of the sense amplifier bands. The sense amplifier power supply lines extend along a row direction in corresponding sense amplifier bands and connected to one another.
The semiconductor memory device according to the first aspect of the present invention further includes: a sense amplifier power supply voltage generation circuit for generating a control voltage; and a plurality of drive circuits provided corresponding to the sense amplifier bands, and activated when sense amplifier circuits of a corresponding sense amplifier band are active, for supplying currents to the corresponding sense amplifier power supply lines according to the control voltage.
A semiconductor memory device according to a second aspect of the present invention includes: a memory array having a plurality of memory cells arranged in rows and columns; a sense amplifier power supply voltage generation circuit for generating an internal power supply voltage; a plurality of sense amplifier circuits each operating using the internal power supply voltage as an operating power supply voltage when activated and each carrying out sensing and amplification of a data of a memory cell on a selected row of the memory array; and a drive circuit for supplying a current to an internal power supply line transmitting the internal power supply voltage when at least one of the plurality of sense amplifier circuits is active.
A drive circuit is provided corresponding to a sense amplifier band and a current is supplied to a corresponding sense amplifier power supply line from the corresponding drive circuit when a sense amplifier circuit of the corresponding sense amplifier band is active and thereby, a current is supplied to a sense amplifier power supply line from the drive circuit in the vicinity thereof independently of a distance from the sense amplifier power supply voltage generation circuit to a corresponding sense amplifier band, so that a delay of response and reduction in voltage caused by interconnection line resistance of the sense amplifier power supply line are suppressed and a voltage on the sense amplifier power supply line can be restored to a predetermined level of voltage at a high speed.
Further, a drive circuit is activated when a sense amplifier circuit is active and a current drive capability of a sense amplifier power supply voltage is made larger equivalently and thereby, with a large current drive capability, the sense amplifier power supply voltage can be supplied to a sense amplifier band at a remote location and reduction in voltage level of the sense amplifier power supply voltage can also be suppressed, with the result that in each of the sense amplifier bands, the sense amplifier power supply voltage at a predetermined level can be supplied in a stable manner.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.